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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:31:55 03/10/2012 
-- Design Name: 
-- Module Name:    InstructionMemory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity InstructionMemory is
    Port ( instr_addr_i : in  STD_LOGIC_VECTOR (9 downto 0);
           instr_cyc_i : in  STD_LOGIC;
           instr_stb_i : in  STD_LOGIC;
			  clr : in STD_LOGIC;
           instr_word_o : out  STD_LOGIC_VECTOR (17 downto 0);
           instr_ack_o : out  STD_LOGIC);
end InstructionMemory;

architecture Behavioral of InstructionMemory is
begin

	iniInstr: process(clr) -- Se podrian cargar las instrucciones desde un fichero...
	begin
		-- vector de interrupcion
		mem(CONV_INTEGER(x"000")) := "111110001000001010"; -- jmp 0x20A
		-- instrucciones del programa
		mem(CONV_INTEGER(x"001")) := "";
		mem(CONV_INTEGER(x"002")) := "";
		-- etc... hasta la pos 0x209
		-- rutina de interrupcion
		mem(CONV_INTEGER(x"20A")) := "";
		mem(CONV_INTEGER(x"20B")) := "";
		-- etc... hasta el max: 0x3FF		
	end process;

	readInstr: process(instr_addr_i, instr_cyc_i, instr_stb_i) is
		type ramtype is array (1023 downto 0) of STD_LOGIC_VECTOR (17 downto 0); -- Con addr de 10 bit hay max 1024 posiciones
		variable mem : ramtype := ((others => (others => '0'))); -- instancia la mem como una variable y la inicializa a 0
	begin	
		if(instr_cyc_i = '1' and instr_stb_i = '1') then -- Si es un ciclo de lectura valido
			instr_word_o <= mem(CONV_INTEGER(instr_addr_i));
			instr_ack_o <= '1';
		else														    -- Si no es un ciclo valido
			instr_ack_o <= '0';
		end if;	
	end process;
	
end Behavioral;

